Integrated circuit memories are organized into one or more arrays each including a matrix of rows and columns, with a memory cell located at each intersection of a row and a column. When accessed during a read cycle, the memory decodes an address to enable one row line. The memory cells on the enabled row line provide their contents onto bit lines, or more commonly, onto differential bit line pairs. Column decoding is used to select a subset of the bit line pairs to connect to one or more differential data line pairs. A sense amplifier connected to each data line pair detects a logic state of the differential signal and amplifies it. The amplified signal may then be provided to an output terminal of the memory, or further decoding may take place.
The speed at which the decoding takes place together with the sense time determines the overall speed of the memory. To help improve the speed of the memory, the sense time may be reduced.
However larger density memories typically employ a sense hierarchy including not only bit lines, but also local data lines and global data lines. In these memories separate sense amplifiers are placed on the local data lines and the global data lines and are enabled in succession to prevent the sense amplifier from consuming excessive power or driving to opposite logic states before recovering. Thus the sequential nature of the local data line sensing and the global data line sensing has limited the ability to decrease access time. Moreover the timing is difficult to achieve since memory designers must design for worst-case conditions.